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preliminary document id# 081xxx date: jan 13, 2003 rev: n version: 1 distribution: public document document id# 081073 date: nov 29, 2004 rev: a version: 1 distribution: public document le8575 dual-resistive, subscriber line interface circuit (slic) device features two channels in a single package serial data interface per-channel powerdown low standby power ( 65 mw per channel) integrated protection no external protection device required battery noise cancellation switchhook detector ring-trip detector switchhook and ring-trip detector self-test fault detector zero ring voltage cross detection three relay drivers per channel 44-pin, surface-mount, plastic package (plcc) ordering information device package LE8575BEJC 44-pin plcc description the le8575 is a dual-resistive, low-cost subscriber line interface circuit (slic) device that is optimized to meet both itu-t recommendations and lssgr requirements for 600 ?/ 900 ?? resistive and complex impedance termination applications. it interfaces the low-voltage circuits on an analog line card to the tip and ring of two subscriber loops. the le8575 does not supply dc current to the subscriber loops? external resistors are used for this purpose. the device is available in a 44-pin plcc package. block diagram relay driver relay driver serial data interface, latches, and logic relay driver relay driver axa ring-trip detector a receive interface and battery noise cancellation a ? + control detectors v bat switchhook and fault detectors a v bat tip current source a ring current source a axb ? + v bat switchhook and fault detectors b ring-trip detector b receive interface and battery noise cancellation b v bat tip current source b ring current source b rdda rdra dgnd v ddd di do clk en rdtb rdrb tsa rsa pta rtpa rtna pra tsb rsb ptb rtpb rtnb prb rgbnb cbnb irpb vrnb xmtb cfltb rgbna cbna irpa vrna v dda agnd v bat xmta cflta nrtb v bat tstb pdb v bat tsta pda nrta nlca nflta relay driver rdra +5d relay driver rddb +5 a v bat npltb nlcb
preliminary 2 le8575 dual-resistive slic device table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 absolute maximum ratings (@ ta = 25 c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 serial interface and logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 resistor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 tip/ring drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 transmit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 battery noise cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 on-hook transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 serial data interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 active state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 test state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 powerdown state with relay driver rdd oper ated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 powerdown state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 ringing state (d2 = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 off-hook detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 ring-trip threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 ring-trip requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 fault detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 zero voltage current cross . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 i/v characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 loop length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 ac design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 codec features and selection summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 design equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 physical dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 44-pin plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
preliminary le8575 dual-resistive slic device 3 list of figures figure 1. power supply rejection vs. frequency diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 2. slic device resistor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 3. le8575 slic device dual-resistive matching requirem ents . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 4. self-test mode circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 5. timing requirements for clk, en, di, and do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 6. logic diagram (positive logic; flip-flops clock ed on high-to-low transition) . . . . . . . . . . . . . . . 21 figure 7. ring-trip threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. ring-trip cir cuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. le8575 slic device i/v template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. equivalent complex terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 11. initial ac interface for complex terminat ion between le8575 slic device and t7504 codec . 28 figure 12. revised ac interface ct and cr combined into a single capacitor cs . . . . . . . . . . . . . . . . . . 29 figure 13. addition of resistor rsc from xmt to irp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 14. typical application diagram with blocking capacitors (cb) included . . . . . . . . . . . . . . . . . . . . . 32 list of tables table 1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2. operating conditions and powering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. battery feed, switchhook detectors (lca and lcb), and fault detectors (flta and fltb) . . . . . 8 table 4. ring-trip detectors (rta, rtb, rz a, and rzb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 5. relay drivers (rdra, rdta, rdrb, rdtb, rdda, and rddb) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 6. analog signal pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7. transmission characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. logic inputs (clk, en, and di) and outputs (do) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. timing requirements for clk, en, di, and do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 10. mmc a31a8575aa thick film resistor module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 11. total module power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 12. truth table for en and clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 13. otuput data bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 14. output data bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 15. input data bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 16. truth table for d1 and d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 17. external components required . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
preliminary 4 le8575 dual-resistive slic device connection diagram pin descriptions symbol type name/function agnd ? analog signal ground. signal ground for channels a and b. cbna i battery noise capacitor (channel a). the current flowing out of pra is ?50 times the voltage applied to cbna, divided by the impedance connec ted between rgbna and agnd. couple v bat to cbna through a high-pass filter to eliminate battery noise from the tip/ring of channel a. cbnb i battery noise capacitor (channel b). the current flowing out of prb is ?50 times the voltage applied to cbnb, divided by the impedance connec ted between rgbnb and agnd. couple v bat to cbnb through a high-pass filter to eliminate battery noise from the tip/ring of channel b. cflta i/o fault filter (channel a). connect a 0.1 f capacitor from cflta to agnd. this capacitor filters tip/ring transients from the channel a fault detector. cfltb i/o fault filter (channel b). connect a 0.1 f capacitor from cfltb to agnd. this capacitor filters tip/ring transients from the channel b fault detector. clk i clock. when the enable input (en) is high, a low-to-high tran sition on this logic input shifts data at the data input pin (di) into the 8-bit serial shift register. when the enable input (en) is low, a low-to-high transition latches the states of the internal detectors into the 8-bit serial shift register. dgnd ? digital ground. ground for channel a and b relay drivers. di i serial data input. data on this logic input is shifted into the 8- bit serial shift register with the clock signal on pin clk. do o serial data output. data in the internal 8-bit serial shift regist er is shifted out on this logic output with the clock signal on pin clk. en i enable. a high-to-low transition on this logi c input latches the data in the 8-bit serial shift register into the output latches. the logic level of en also controls which data is shifted into the 8-bit serial shift register (refer to clk pin description). this pin has a 100 k internal pull-up resistor to vddd. irpa i receive current positive input (channel a). the differential current flowing from pta to pra is 200 times the current flowing into irpa. irpb i receive current positive input (channel b). the differential current flowing from ptb to prb is 200 times the current flowing into irpb. nc ? no connect. unused pin (no internal connection). rdra rtpa rdta xmta tsa rsa rgbna vrna rtpb rdtb rdrb xmtb tsb rsb rgbnb vrnb 7 9 10 11 12 13 14 15 16 17 8 6 4 3 2 1 4443424140 5 18 20 21 22 23 24 25 26 27 28 19 39 37 36 35 34 33 32 31 30 29 38 rddb rtnb rtna pta pra agnd cbna cbnb agnd ptb prb vddd di nc cfltb clk do en dgnd cflta vddd dgnd rdda irpa irpb 44-pin plcc vbat vdda vbat
preliminary le8575 dual-resistive slic device 5 pra o protected ring (channel a). output of the ring current drive amplifier a. connect pra to the ring of loop a through an overvoltage protection resistor (1.4 k ? minimum). prb o protected ring (channel b). output of the ring current drive amplifier b. connect prb to the ring of loop b through an overvoltage protection resistor (1.4 k ? minimum). pta o protected tip (channel a). output of the tip current drive amplifier a. connect pta to the tip of loop a through an overvoltage protection resistor (1.4 k ? minimum). ptb o protected tip (channel b). output of the tip current drive amplifier b. connect ptb to the tip of loop b through an overvoltage protection resistor (1.4 k ? minimum). rdda o disconnect relay driver (channel a). this output drives an external relay. rddb o disconnect relay driver (channel b). this output drives the external relay. rdra o ringing relay driver (channel a). this output drives the external ringing relay. rdrb o ringing relay driver (channel b). this output drives an external ringing relay. rdta o test relay driver (channel a). this output drives an external test relay. rdtb o test relay driver (channel b). this output drives an external test relay. rgbna i battery noise gain resistor (channel a). the current flowing out of pra is 50 times the current flowing into rgbna. connect a resistor from rgbna to agnd to set the gain of the channel a battery noise cancellation circuit. rgbnb i battery noise gain resistor (channel b). the current flowing out of prb is 50 times the current flowing into rgbnb. connect a resistor from rgbnb to agnd to set the gain of the channel b battery noise cancellation circuit. rsa i ring sense (channel a). positive input of channel a transmit op amp. connect one high-value resistor between rsa and the ring of loop a and another high-value resistor between rsa and agnd. rsb i ring sense (channel b). positive input of channel b transmit op amp. connect one high-value resistor between rsb and the ring of loop b and another high-value resistor between rsb and agnd. rtna i ring-trip negative (channel a). negative sense input for the ring-trip detector. rtmb i ring-trip negative (channel b). negative sense input for the ring-trip detector. rtpb i ring-trip positive (channel b). positive sense input fo r the ring-trip detector. tsa i tip sense (channel a). negative input of channel a transmit op amp. connect one high-value resistor between tsa and the tip of loop a and another high-value resistor between tsa and xmta. tsb i tip sense (channel b). negative input of channel b transmit op amp. connect one high-value resistor between tsb and the tip of loop b and another high-value resistor between tsb and xmtb. vbat ? office battery supply. negative office battery su pply for channels a and b. vdda ? 5 v analog dc supply. vddd ? 5 v digital dc supply. 5 v supply for logic and re lay driver flyback diodes. vrna i receive voltage negative input (channel a). the differential current flowing from pta to pra is ?200 times the voltage applied to vrna, divided by the impedance connected between irpa and agnd. vrnb i receive voltage negative input (channel b). the differential current flowing from ptb to prb is ?200 times the voltage applied to vrnb, divided by the impedance connected between irpb and agnd. xmta o transmit signal output (channel a). channel a transmit amplifier output. xmtb o transmit signal output (channel b). channel b transmit amplifier output. symbol type name/function
preliminary 6 le8575 dual-resistive slic device absolute maximum ratings (@ t a = 25 c) stresses in excess of the absolute maximum ratings can ca use permanent damage to the dev ice. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in th e operational sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. note: analog and battery voltages are referenced to ag nd; digital (logic) voltages are referenced to dgnd. the ic can be damaged unless all ground connections are applied be fore, and removed after, all other connections. furthermore, when powering the device, the user must guarantee that no external potenti al creates a voltage on any pin of the device that e xceeds the device ratings. some of the known exampl es of conditions that cause such potentials during powering are (1) an inductor connected to ti p and ring that can force an overvoltage on v bat through external components if the v bat connection chatters, and (2) inductance in the v bat lead that could resonate with the v bat filter capacitor to cause a destructive overvoltage. electrical characteristics generally, minimum and maximum values are testing requirements. however, some parameters may not be tested in production because they are guaranteed by design and de vice characterization. typical values refl ect the design center or nominal value of the parameter; they are for information only and are not a requirement. minimum and maximum values apply across the entire temperature range (?40 c to +85 c) and entire battery range (?42 v to ?58 v). un less otherwise specified, typical values are defined as 25 c, v dda = 5 v, v ddd = 5 v, v bat = ?48 v. positive currents flow into the device. table 1. absolute maximum ratings parameter symbol min value max unit 5 v analog dc supply v dda ?0.5 ?+7.0v 5 v digital dc supply v ddd ?0.5 ? +7.0 v office battery supply v bat ?65 ? +0.5 v logic input voltage ? ?0.5 ? v ddd + 0.5 v logic input clamp diode current, per pin ? ? 20 ? ma logic output voltage ? ?0.5 ? v ddd + 0.5 v logic output current, per pin (excluding relay drivers) ? ? 35 ? ma maximum junction temperature ? ? 150 ? c operating temperature range ? ?40 ? +125 c storage temperature range t stg ?40 ? +125 c relative humidity range ? 5 ? 95 % ground potential difference (dgnd to agnd) ? +0.5 ? ?0.5 v
preliminary le8575 dual-resistive slic device 7 table 2. operating conditions and powering parameter min typ max unit temperature range ?40 ? 85 c humidity range 5 ? 95 1 %rh supply voltage: v dda v ddd v bat v dda ? v ddd 4.75 4.75 ?42 ? ? ? ?48 ? 5.5 5.5 ?58 0.5 v v v v supply currents (both channels active): i vdda + i vddd (5 v) i vbat (?48 v) 2 ? ? ? ? 19.0 ?27.5 ma ma supply currents (both channels powerdown): i vdda + i vddd (5 v) i vbat (?48 v) 2 ? ? ? ? 18.0 ?2.0 ma ma total power dissipation (5 v; ?48 v) 3 : active (both channels) powerdown (both channels) ? ? ? ? 1.40 185 w mw power-supply rejection 4, 5 (50 mvrms ripple): tip/ring and xmt refer to figure 1 . thermal 5 : thermal resistance (still air) operating tjc ? ? ? ? 47 155 c/w c 1. not to exceed 26 grams of water per kilogram of dry air. 2. includes v bat current through the external dc feed resistors, assuming the loop is open. 3. includes power dissipation in the external dc feed resistors per application diagram, assuming the loop is open. 4. v bat power supply rejection depends on the battery noise cancellation circuit. the performance stated here applies only during the active state and assumes proper battery noise cancellation, i.e., a high-pass filter from v bat to cbn and a resistor from rgbn to agnd which is 50 times the dc feed resistor connecting v bat to ring (refer to the application diagram). 5. this parameter is not tested in production. it is guaranteed by design and device characterization.
preliminary 8 le8575 dual-resistive slic device table 3. battery feed, switchhook detectors (lca and lcb), and fault detectors (flta and fltb) parameter min typ max unit loop resistance range 1 : (3.17 dbm overload into 600 ? ) i loop = 18 ma at v bat = ?48 v 1800 ? ? ? longitudinal current capability per wire 8.5 ? ? marms switchhook detector loop resistance 2 : off-hook (lc = 1) on-hook (lc = 0) ? ? 4800 4000 ? ? ? 3200 ? ? ? ? fault detector 2, 3 : | v tip | or | v ring ? v bat | no fault (flt = 0) fault (flt = 1) detection delay t det (no fault to fault; cflt = 0.1 f) release delay (fault to no fault; cflt = 0.1 f) ? 39 10 1.6 t det 36 36 ? ? 33 ? 30 2.5 t det v v ms ms 1. assumes 2 x 300 ? external dc feed resistors. 2. detector values are independent of office battery and are valid over the entire range of v bat . 3. fault voltage is defined as the absolute value of the dc voltage across either dc feed resistor. if the voltage across either feed resistor exceeds this value, a fault is determined to be present. flt is forced to a 0 when d2 = 1 (ringing state). table 4. ring-trip detectors (rta, rtb, rza, and rzb) parameter min typ max unit ringing source 1 : frequency ( ? ) dc voltage ac voltage 19 ?39.5 60 20 ? ? 28 ?57 105 hz v vrms ring trip 2, 3 (rt = 1): loop resistance trip time ( ? = 20 hz) rt valid 2000 ? ? ? ? ? ? 200 80 ? ms ms ringing source zero crossing (referenced to v bat /2): ringing voltage positive (rz = 1) ringing voltage negative (rz = 0) 3v bat /4 ? ? ? ? v bat /4 v v 1. the ringing source consists of the ac and dc voltages added together (battery-backed ringing); the ringing return is ground. 2. rt must also indicate ring-trip when the ac ringi ng voltage is absent (<5 vrms) from the ringing source. 3. pretrip: ringing must not be tripped by a 10-k ? resistor in parallel with an 8- f capacitor applied across tip and ring.
preliminary le8575 dual-resistive slic device 9 relay drivers the relay drivers operate using the v ddd supply. when v ddd is first applied to the device, the relay drivers must power up and remain in the off-state until the slic device is configured via the serial data interface. the table below summarizes their parameter requirements. table 5. relay drivers (rdra, rdta, rdrb, rdtb, rdda, and rddb) parameter 1 symbol min max unit off-state output current (v out = v ddd )i off ? 10 a on-state output voltage (i out = 40 ma) v on 0 0.60 v on-state output voltage (i out = 20 ma) v on 0 0.40 v clamp diode reverse current (v out = 0) i r ? 10 a clamp diode on voltage (i out = 80 ma) v oc v ddd + 0.5 v ddd + 3.0 v turn-on time 2 t on ? 10 s turn-off time 2 t off ? 10 s 1. unless otherwise specified, all l ogic voltages are referenced to dgnd. 2. this parameter is not tested in production. it is guaranteed by design and device characterization.
preliminary 10 le8575 dual-resistive slic device table 6. analog signal pins parameter min typ max unit pta, ptb, pra, and prb: surge current (from external source): continuous 1 ms exponential pulse (50 repetitions) 1 second, 60 hz (60 repetitions) 10 s rectangular pulse (10 repetitions) ? ? ? ? ? ? ? ? 50 750 175 1.25 ma dc ma marms a output drive (pta and ptb): drive current (sink only) voltage swing (i out = 15 ma) dc bias current (active state only) 0.1 v bat + 4 5.3 ? ? 5.6 15 agnd 5.9 ma v ma output drive (pra and prb): drive current (source only) voltage swing (i out = 15 ma) dc bias current (active state only) ?15 v bat ?5.3 ? ? ?5.6 ?0.1 agnd ? 4 ?5.9 ma v ma output impedance (60 hz?3.4 khz) 1 output load resistance (dc or ac) 1 1 0 ? ? ? 100 m ? k ? xmta and xmtb: output drive current output voltage swing (3 ma load): maximum minimum 3 v bat v bat + 10 ? ? ? ? v dda +2.5 ma v v output short-circuit current 2 output impedance (60 hz?3.4 khz) output load dc resistance output load ac impedance 1 output load capacitance 1 ? ? 20 2 ? ? ? ? ? ? 30 10 ? ? 50 ma ? k ? k ? pf vrna and vrnb: input voltage range input bias current input impedance 1 ?1.75 ? 20 ? ? ? 3.5 1 ? v a m ? irpa and irpb: input offset voltage (to respective vrn) input impedance ? ? ? ? 10 5 mv ? cbna and cbnb: input voltage range input bias current input impedance ?1.75 ? 50 ? ? ? 3.5 250 ? v na m ? tsa, tsb, rsa, and rsb: surge current (from external source) input voltage range input bias current differential input impedance 1 common-mode input impedance 1 external capacitance (67 k ? source impedance) 1 ? v bat + 3 ? 50 50 ? ? ? ? ? ? ? 25 agnd 1 ? ? 10 madc v a k ? m ? pf 1. this parameter is not tested in production. it is guaranteed by design and device characterization. 2. a v bat or ground short on xmta or xmtb will not cause a device failure.
preliminary le8575 dual-resistive slic device 11 transmission transmit direction is tip/ring to xmt. re ceive direction is irp/vrn to tip/ring. table 7. transmission characteristics parameter min typ max unit longitudinal balance ( ieee 1 std. 455?1976) 2 : 50 hz?1 khz 1 khz?3 khz 54 50 70 66 ? ? db db metallic to longitudinal balance 2 : 200 hz?4 khz 30 ? ? db rfi rejection 3 : (0.5 vrms, 50 ? source, 30% am mod. 1 khz) 500 khz?10 mhz 10 mhz?100 mhz ? ? ? ? ?65 ?45 dbv dbv tip/ring signal level ? ? 3.17 dbm ac termination impedance 4 ? 600 ? ? total harmonic distortion (200 hz?4 khz) 3 ? ? 0.3 % transmit gain ( ? = 1 khz) 5 : tip/ring to xmt ?0.486 ?0.500 ?0.514 ? receive gain ( ? = 1 khz): irp current to differential current flowing from pt to pr vrv to irp 195 0.995 200 1 205 1.005 ? ? cbn gain ( ? = 1 khz): 1 rgbn current to current flowing cbn to rgbn ?49.5 0.995 ?50 1 ?50.5 1.005 ? ? gain vs. frequency (transmit & receive; 1 khz reference) 3 : 200 hz?3.4 khz ?0.1 0 0.1 db gain vs. level (transmit & receive; 0 dbv reference) 3 : ?50 db to +3 db ?0.05 0 0.05 db interchannel crosstalk 3 : 200 hz?3.4 khz ? ? 77 db idle-channel noise (tip/ring; 600 ? termination): psophometric 3 c-message 3 khz flat 3 ? ? ? ? ? ? ?77 12 20 dbmp dbrnc dbrn idle-channel noise (xmt; 600 ? termination): psophometric 3 c-message 3 khz flat 3 ? ? ? ? ? ? ?77 12 20 dbmp0 dbrnc0 dbrn0 1. ieee is a registered trademark of the institute of electrical and electr onics engineers, inc. 2. assumes ideal external components. 3. this parameter is not tested in production. it is guaranteed by design and device characterization. 4. transmission characteristics are specified assuming a 600 w resistive te rmination; however, fe edback using external components allows the user to adjust the termination impedance from the intrinsic 600 w of the feed resistors to most itu-t recommended complex termination impedances. 5. measured with the le8575 slic device connected per app lication diagram with ideal external components.
preliminary 12 le8575 dual-resistive slic device serial interface and logic the tables below summarize the parameter and timing requirements for logic inputs clk, en, di, and do. table 8. logic inputs (clk, en, and di) and outputs (do) parameter 1 symbol min max unit high-level input voltage v ih 2v ddd v low-level input voltage v il 0 0.8 v input bias current (high and low), clk and di i in ? 50 a input bias current (high), en i in ? 50 a input bias current (low), en (vin = 0 v) i in ?20 ?100 a high-level output voltage (i out = ?100 a) v oh v ddd ? 1.5 v ddd v low-level output voltage (i out = 180 a) v ol 0 0.4 v output short-circuit current (v out = v ddd ) i oss 1 35 ma output load capacitance 2 c ol 0 50 pf 1. unless otherwise specified, all logic voltages are referenced to dgnd. 2. this parameter is not tested in production. it is guaranteed by design an d device characterization. table 9. timing requirements for clk, en, di, and do parameter 1 symbol min max unit input rise and fall time, clk & en (10% to 90%) 2 t r , t f 070ns maximum input capacitance 2 c in ?5pf maximum clk frequency (50% duty cycle) f max ?1.25mhz propagation delay, clk to do 2 t pco 0 350 ns propagation delay, en to rd outputs 2 t pcr 010 s minimum setup time from di to clk 2 t sdc 150 ? ns minimum setup time from di to en 2 t sde 150 ? ns minimum setup time from en to clk 2 t sec 150 ? ns minimum hold time from clk to di 2 t hdc 50 ? ns minimum hold time from en to clk 2 t hec 50 ? ns minimum pulse width of clk t wck 400 ? ns minimum pulse width of en t wen 800 ? ns 1. unless otherwise specified, all times are meas ured from the 50% point of logic transitions. 2. this parameter is not tested in production. it is guaranteed by design an d device characterization.
preliminary le8575 dual-resistive slic device 13 figure 1. power supply rejection vs. frequency diagram applications general the le8575 is a dual (channels a and b) slic device. each chan nel operates independently such that no interaction occurs between the channels. the following description applies to both channels though the description may refer to only a single channel. some circuits, such as reference circuits which do no t impact interchannel crosstalk, are common to both channels. the le8575 device supplies a precise differential current to the ti p/ring pair (via pt and pr) as a function of analog signal voltages on irp and vrn. however, the current drivers connected to pt and pr are not designed to supply dc feed current to the loop. two external resistors (typically 300 ? ), connected to office battery and ground, must be used in conjunction with the le8575 slic device to provide dc loop current. these resistor s will primarily determine the longitudinal balance of the line fe ed; thus, they must be matched appropriat ely to meet the longitudinal balance requirements (0.4% for 50 db balance). these resistors also have a significant im pact on the termination impedance of the slic device. feedback, using external components, allows the user to adjust th e termination impedance from the intrinsic 600 ? of the feed resistors to most itu-t recommended complex termination impedances. since the le8575 d oes not supply dc to the loop, outputs pt and pr can be coupled to the tip and ring through a resistance high enough to al low for simple lightning protec tion of the drivers. however, the resistance must be low enough to achieve the coupling of suffic ient ac signals to the tip and ring from the available power supply. since the tip and ring drivers are current sources, the value of the resistance is arbi trary and does not affect the performance of the slic device. a minimum value of 1400 ? is required for protection purposes. the le8575 also senses the tip voltage, ring voltage, and diff erential tip/ring voltage via the ts and rs sense inputs. the differential dc voltage is used internally for switchhook dete ction. the tip and ring voltages are also used internally to dete ct faults on tip and ring. both detector thresholds are preset inte rnally. the status of each detector is monitored at pin do by reading the 8-bit serial shift register. the differenti al tip/ring ac signal appears on analog output xmt. 10 1 ?40 ?30 ?20 ?10 0 frequency (hz) psrr (db) ?50 ?60 10 2 10 3 10 4 10 5 10 6 v dda (metallic) v bat (metallic)
preliminary 14 le8575 dual-resistive slic device the le8575 also includes: ? per-channel ring-trip detectors, loop closure detectors ? six relay drivers (three per channel) ? eight-bit serial-to-parallel and parallel-to-serial logic interface ? per-channel circuits which eliminate the battery noise that is coupled to the tip and ring through the dc feed resistors ? fault detection ? zero ring voltage detection resistor module the le8575 requires certain external resistors at the tip and ri ng interface. because of matchi ng and protection requirements, one of the most economical options recommended to implement thes e registers is in a thick film resistor module. a schematic and a brief description of the function of each of these resistor s is given in figure 4. note that microelectronic modules corporation mmc ? a31a8575aa thick film resistor module is an applicat ion-specific resistor module designed for use with the le8575 slic device. the values, tolerance, matching, and power rating of the mmc a31a8575aa module are given in table 10. resistors r 1 and r 2 are the dc feed resistors. r 1 is connected from battery to ring, and r 2 is connected from tip to ground. the dc loop current is fed to the subscriber loop via these re sistors. these resistors will set the dc i/v template of the line circuit with the i/v template being linear with a ?1/600 w slope. no cons tant current region at short dc loops is provided by resistors r 1 and r 2 , or the le8575 slic device. note: for additional information, contact microel ectronic modules corporation (mmc), 2601 s. moorland road, new berlin, wi 53151. usa: (414) 785-6506, fax (414) 785-6516. figure 2. slic device resistor module note: pin numbers are mmc a31a8575aa pin numbers. resistors are label ed per mmc a31a8575aa description. nodes are le8575 slic device package nodes. note: for 50 db longitudinal balance, 0.2% for 58 db balances. continuous power (rms). table 10. mmc a31a8575aa thick film resistor module resistor value tolerance power surge rating r 1 300 ? 1.0% 2.0 w lightning: power cross r 2 300 ? 1.0% 2.0 w lightning: power cross r 3 100 k ? 1.0% 250 mw none r 4 100 k ? 1.0% 250 mw none r 5 200 k ? 1.0% 250 mw lightning: power cross r 6 200 k ? 1.0% 250 mw lightning: power cross r 7 1.4 k ? 2.0% 0.5 w lightning: power cross r 8 1.4 k ? 2.0% 0.5 w lightning: power cross r 9 15 k ? ? 10 mw none r 9 /r 1 50 1.0% ? ? r 1 /r 2 1 0.35% ? ? (r 3 + r 6 )/(r 4 + r 5 ) 1 0.35% ? ? tip 15 fuse tip 19 17 r 7 6pr ring r 1 v bat r 9 rgbn gnd r 3 rs 10 9 8 7 5 fuse ring 1 3 r 4 ts xmt 12 11 r 5 r 2 r 8 r 6 gnd 13 pt 14
preliminary le8575 dual-resistive slic device 15 resistors r 1 and r 2 also provide a common-mode impedance of (300 || 300) 150 ? . these resistors will primarily determine the longitudinal balance of the line circuit; thus they must be matched appropriately to meet longitudinal balance requirements (0.35% for 50 db and 0.2% for 58 db). also, they have a significant impact on t he termination impedance of the slic device. feedback using external components (external components when a first- or second-generation codec is used) allows the user to set the termination impedance at 600 ?, or most itu-t recommended complex termination impedances. resistors r 1 and r 2 , along with r 3 and r 7 , are used in conjunction with the self-test feature of the le8575 sl ic device. in this mode, the ring current drive amplifier is sa turated to ground, and the tip amplifier is saturated to battery, which causes both the ring-trip and loop closure detectors to trip. ring-trip and loop closure detector output are bits rt and lc, respectively, in t he serial output stream. under normal operating conditions, resistors r 1 and r 2 will see the battery voltage less the tip/ring voltage. assuming a tip/ ring voltage of 6 v (representative of a short into a handset), the nominal continuous operating power of r 1 and r 2 is given by: (48 v ? 6 v) 2 /600 ? = 2.94 w per r 1 and r 2 resistor pair 2.94 w/2 = 1.47 w per resistor the operating power rating of r 1 and r 2 is 2 w. this is the steady-state power rating of r 1 and r 2 , and it is adequate for normal operating conditions. the ability of these resistors to withsta nd fault conditions depends on the power ratings of the individu al resistors and on the power rating of the thick film resistor modul e itself. obviously, the higher the power capabilities of the resistor module, the less susceptible the resistors are to damage during faults. the various fault conditions are discussed further in t he protection section of this data sheet. resistors r 3 and r 6 set the gain of the slic device in the transmit (2-wire to 4-wire) direction. this is shown in figure 3 . figure 3. le8575 slic device dual-resistive matching requirements the matching of resistors r 3 and r 6 will determine the gain accuracy of the slic dev ice; therefore, these re sistors must also be matched accordingly. the matching requirements are given in ta b l e 9 . because of the high resistance values, the normal operating power of resistors r 3 through r 6 will be relatively low. given design margin and thick film technology capabilities, a power ra ting of 250 mw for these resi stors is not unreasonable. resistors r 7 and r 8 are used to couple the pt and pr current drive amplif iers to tip and ring. since the pt and pr drive amplifiers are current sources, the value of the series resistan ce does not affect the loop length or other performance of the slic device, and may be arbitrarily high for protection purposes. a value of 1.4 k ? is adequate for protection purposes. under normal operating conditions, these resistors will see the battery voltage less the tip/ring voltage. assuming a tip/ring voltage of 6 v (representative of a short into a ha ndset), the nominal conti nuous operating power of r 7 and r 8 is given by: (48 v ? 6 v) 2 /2.8 k ? = 0.630 w per r 7 and r 8 resistor pair 630 mw/2 = 315 mw per resistor (r 7 and r 8 8 ) hence, the operating power rating of 500 mw for r 7 and r 8 . this is the nominal rating for r 7 and r 8 under normal operating conditions. again, the ability of these resistors to withstand fault conditions depends on the power rating. resistor r 9 is also included on the thick film resistor module. this resi stor is used to set the gain of the battery noise cancellation circuit. see the battery noise cancellation section of this data sheet for design equations to set the value of r 9 . ? + tip ring r 5 200 k ? r 6 200 k ? r 3 100 k ? xmt r 4 100 k ?
preliminary 16 le8575 dual-resistive slic device protection because of the resistive feed architecture , a simple inexpensive protection scheme t hat does not require a separate external protection device may be used. the mmc a31a8575aa resistor module has specif ications which are qualified to bellcore gr-core-1089, ul ? 1459, ul 497a, fcc part 68.302 (d) & (e) and rea form 397g, itu-t k20, and itu-t k21. lightning and power cross protection are provided by the two dc feed resistors, r 1 and r 2 , in the external resistor module. under fault conditions, these resistors serve as fault current-limiting resistors. fault curr ent is steered to ground and to battery via resistors r 1 and r 2 , respectively. thus, the battery design must be such that the various specified faults can be applied to the battery through 300 ?, without damaging the battery or the line circuit. resistors r 1 and r 2 need to be designed to survive lightning surges and to dissipate power associated with a ring ground dc fault and specified ac power cross faults?both a sneak under and full surge type fault. under certain sustained fault condition s, r 1 and r 2 could fail when they are required to survive. for this reason, a per-channel fault detector is included on the le8575 slic device. when the voltage across either r 1 and/or r 2 is greater than a nominal 36 v, the fault detect bit (flt) in the serial data output will go high. the control logic on the line card detects flt is high, and opens an external electromechanical relay (emr) to isolate the resistors from the loop, enabling the resi stors to service extended power cross. (not e the emr is the test in or test out e mr, and this relay is driven by one of the inte rnal relay drivers on the le8575 slic device.) a delay of 10 ms to 30 ms is provided (using an external capaci tor on pin cflt) in the fault detector. this prevents transients on the tip and ring from tripping the faul t detector when a fault is not present. the tip/ring drive amplifiers, which feed the ac signal to n odes pr and pt, are high-impedance current drivers. since these nodes are current sources, the value of protection current-limiti ng series resistance does not af fect the loop length or other slic device performance, and may be arbitr arily high for protection purposes. resistors r 7 and r 8 in the resistor module are used for this purpose. these resistors have a value of 1.4 k ? with a power rating 0.5 w. internal diodes clamp nodes pr and pt to ground and battery. the voltage sense leads, rs and ts, are also exposed to the ou tside plant. current to these nodes is limited by resistors r 3 and r 4 in the resistor module. resistors r 3 and r 4 are 100 k ? , 250 mw resistors. internal diodes also clamp nodes rs and ts to ground and battery. the ability of the resistors to survive faults is a function of the power dissipated in the individual resistors and the total power dissipated on the entire thick film module. fault conditions include: ? a continuous worst-case (fault detector) sneak under condition of 39 v dc applied metallically to ring in the case of a ring ground fault, and ? a sneak under condition of 39 vp (voltage peak) applied to tip and ring, as described in bellcore 1089, itu-t k20, in the case of power cross. additionally, there is a transient fault co ndition, assuming full specified power cros s fault voltages (e.g., bellcore 1089, it u-t k20) for a time duration equal to the maximum response time that it will take to isolate the line circuit from the fault via the fau lt detector and emr described above. for example, a ring ground fault assuming fault detector s neak under will result in a worst-case potential across the r 1 of 39 v. the power dissipated in r 1 under this condition is calculated as follows: (39 v * 39 v)/300 ? = 5 w since this is a sneak under condition, the fault detector will not trigger and the time duration of the fault can be infinite. in the case of a longitudinally applied sneak under power cross, the maximum voltage seen, this time by both r 1 (ring) and r 2 (tip), is 39 vp (voltage peak). the power dissipation is given by: maximum voltage = 39 vp = 27.6 vrms maximum power = (27.6 v rms * 27.6 vrms)/(300 ? ) = 2.54 w per resistor. thus, 2.54 w will be dissipated per re sistor or a total of 5.1 w in a longitudinal sneak under condition. if r 1 and r 2 are rated for 2 w, they can fail und er these fault conditions. also, the mmc a31a8575aa resistor module includes a fail-safe thermal fuse located at the tip and ring nodes (pin 1 and pin 19) of the module for this reason. a fail-safe fuse i s recommended for any resistor module used with the le8575 slic device. with thick film technology, not only is the power capabilities of the individual resistors important, but also the power handli ng capabilities of the entire module. the total module power dissipa tion is calculated by summing the power dissipation for each o f the resistors under a given condition.
preliminary le8575 dual-resistive slic device 17 for example, the module power dissipation for the above sneak under fault conditions is calculated in table 11. thus, the hic will require a minimum power rating of 6 w continuous to survive thes e sneak under conditions. similar consideration to the individual resistor and total module power capability should be given to full voltage power faults , but taking into account the fault detector will isolate the slic device and resistor module after some finite period of time. the f ault detector indicates a fault in the serial data output stream in 10 to 30 ms. recognition and relay activation time need to be considered. tip/ring drivers each channel of the le8575 utilizes a current source for the tip/ ring driver. the driver is capabl e of sinking (but not sourcin g) up to 15 ma from the tip (pt) while swinging to within 4 v of office battery (v bat ), and sourcing (but not sinking) up to 15 ma to the ring (pr) while swinging to within 4 v of ground (agnd). sinc e the current driver is not bidirectional, during transmission (powerup) each lead is biased at 5.6 ma dc. receive interface the receive interface circuitry couples the differential signal on receive inputs irp and vrn to the tip/ring drivers. input ir p is a low-impedance (<5 ? ) current input while vrn is a high-impedance voltage input. internal feedback forces the voltage at irp to be equal to vrn such that a voltage applied to vrn causes a current flow out of irp, which equals that voltage divided by th e impedance connected from irp to agnd (assuming the input voltage is referenced to agnd). the receive interface and tip/ring drivers provide a current gain of 200, i.e., a differential out put current flows from pt to pr which is 200 times the current flowing into irp. the receive in terface also provides a level shift since the inputs, irp and vr n, are referenced to analog ground, while the outputs, pt and pr, swing between agnd and v bat . the receive interface ensures that the input current is not converted to a common-mode current at pt and pr. transmit interface the transmit interface circuitry interfaces the differential voltage on tip and ring to transmit output xmt. the tip/ring diffe rential voltage (both ac and dc) appears on output xmt with a gain of 0.5. the transmit interface uses an operational amplifier with four external resistors to perform a differential to single-ended conversion. output xmt is referenced to ground (agnd). the longitudinal balance and gain accuracy at xmt depends on the matching of the external resistors. because a large dc potential exists at xmt, a capacitor must be used to couple the ac signal to the low-voltage codec circuitry . the operational amplifier inputs are ts and rs. these inputs are also used by the fault-detectio n circuitry to detect fault vol tages on tip or ring. a fault is detected when the magnitude of the voltage across either dc feed resistor exceeds a nominal 36 v (equivalent to approximately 4 w dissipation in either resistor). a delay is provided (using an external capacitor on pin cflt) in the fault detector. this prevents transients on tip and ring from tripping the fault detector when a fault is not actually pres ent. battery noise cancellation the battery noise cancellation circuit senses the ac noise on the battery via the capacitor connected from input cbn to v bat . it then couples this noise, 180 degrees out of phase, to the ring curre nt driver amplifier. this ca ncels the battery noise that is coupled to the ring through the feed resistor connected to v bat . table 11. total module power dissipation resistor (r) value ( ? ) ring ground maximum dc fault voltage (v) ring ground maximum dc fault power (w) longitudinal fault maximum peak voltage (vp) longitudinal fault maximum rms voltage (vrms) longitudinal fault maximum rms power (w) 1 300 39 5.07 39 27.577 2.535 2 300 0 0 39 27.577 2.535 3 100 k 29 0.015 39 27.577 0.0076 4 100 k 0 0 39 27.577 0.0076 5 200 k 39 0.0076 39 27.577 0.0038 6 200 k 0 0 39 27.577 0.0038 7 1.4 k 39 1.086 39 27.577 0.543 8 1.4 k 0 0 39 27.577 0.543 total hic power: 6.18 ? ? 6.18
preliminary 18 le8575 dual-resistive slic device additionally, it ensures longitudinal balance which depends only on the matching of the battery feed resistors by creating an a c ground at v bat with respect to signals on the ring lead. for the cancellation to operate properly, both the phase and gain must be accurate. the battery noise cancellation gain is a transconductance that is equal to 50 divided by resistor r9 on the thick film resistor module connected from rgbn to ground (agnd). this value must be equal to the re ciprocal of the dc f eed resistor (1/300 ? ), that is, it is advantageous if the two resistors ar e matched and tracked thermally, i.e., loca ted on the same film integrated circuit (f ic). on-hook transmission in powerup mode, the le8575 slic device provides a dc bias of 5.6 ma. the 5.6 ma bias is also present under on-hook conditions. the le8575 slic device is able to support on-hook tran smission because of this bias. it is sufficiently high to dri ve a 3.17 dbm signal into a 600 ? or 900 ? loop under open-circuit conditions. an inter nal current source provides a dc bias of 112 a. there is an internal current gain of 50; thus (50 ?112 a) 5.6 ma flows from battery through r 1 to pr, and 5.6 ma flows from pt through r 2 to ground under on-hook conditions. self-test the le8575 slic device offers a self-test capability. this is set via logic inputs d1 and d0 in the serial input data stream. i n this mode, shown in figure 6, the ring current dr ive amplifier is saturated to ground, and the tip amplifier is saturated to battery , which causes both the ring-trip and loop closure detectors to indicate an off-hook condition. in this operation mode, the ring relay must not be active. the ring relay driver output in the le8575 is at package nodes rdr (a&b). these relay drivers are controlle d by logic inputs d2 (a&b) in t he serial input data stream. see table 13 for details. figure 4. self-test mode circuit serial data interface a 4-wire serial interface (di, do, clk, and en) is used to pa ss data from the control logic on the line card to the le8575 slic device, and to pass detector information fr om le8575 slic device to the control logic on the line card. when enable input en is high, data on input di is clocked into an 8-bit shift regi ster on a high-to-low transition of the clock input clk. eight latches (four per channel) are provided to store the data. data is loaded into the eight la tches from input di and the fi rst 7 bits of the shift register on the high-to-low transition of en. wh en en is low, a high-to-low transition on clk loads all of th e 50 r 9 ----- - 1 300 ? ------------- = r 9 15 k ? = + ? lca/b + ? rta/b pr ptp rtn 200 k ? 200 k ? 1.4 k ? r 1.0 m ? 0.1 f 1.0 m ? 8.25 m ? 300 ? v ring v bat 100 k ? pt t 1.4 k ? 100 k ? 300 k ?
preliminary le8575 dual-resistive slic device 19 detector information (loop closure, fault zero voltage, and ring -trip from the internal detector circuitry) into the 8-bit shift register. when en is high, data in the 8-bit shift regist er is clocked out on output do on the high-to-low transition of clk. two latch outputs per channel drive relay drivers. the drivers are included on the le8575 slic device. these are the relay driv ers whose outputs are at external package nodes rdr (a&b) and rdt (a&b). the remaining two latch output power channels are internal control signals. these are logic data bits d0 (a&b) and d1 ( a&b). these bits input to a co mbinational l ogic circuit th at controls the operational stat e of each channel and also controls the state of the third relay driver. the third relay driver?s output is at external package node rdd (a&b). refer to the truth table ( table 14 ) for more details. note that up to 16 channels may be daisy-chained together. the do lead of package 1 (channels 1 and 2) may be tied to the di lead of package 2 (channels 3 and 4), for example. all en and clk should also be tied together in this mode. the le8575 slic device device has an internal reset which guaran tees that all relay drivers power up in the off-state when 5 v (v ccd and v cca ) is applied to the device. this reset operates properl y only if input en is held high (within 0.5 v of v ccd ) when the 5 v is applied. an external pull-up resistor from the en bus to v ccd satisfies this requirement, pr ovided that the logic-driving en does not pull the en bus low during powerup. figure 5 shows the timing characteristics and requirement definitions. figure 5. timing requirements for clk, en, di, and do table 12. truth table for en and clk en clk function 1 ? shift register clocked, qn = qn ? 1; latches unaffected. 0 ? channel data latched into shift register; latches unaffected. ? x contents of shift register transferred to output latches. table 13. otuput data bit definition data bit output output bit definition d0a d0a latch output state d0a (refer to operating states section). d1a d1a latch output state d1a (refer to operating states section). d2a rdra ringing relay driver a is on (rdra low = relay energized) when d2a = 1. d3a rdta test relay driver a is on (rdta low = relay energized) when d3a = 1. d0b d0b latch output state d0b (refer to operating states section). d1b d1b latch output state d1b (refer to operating states section). d2b rdrb ringing relay driver b is on (rdrb low = relay energized) when d2b = 1. d3b rdtb test relay driver b is on (rdtb low = relay energized) when d3b = 1. di en clk do t sde t wen t hdc t sdc t hec t sec t wck t wck t pco
preliminary 20 le8575 dual-resistive slic device table 15. input data bit definition table 14. output data bit definition data bit output output bit definition rza d0a channel a ringing voltage zero cr ossing detector output (positive = 1). flta d1a channel a fault detector output (loop fault = 1). rta d2a channel a ring-trip detector output (ring-trip = 1). lca d3a channel a switchhook detector output (off-hook = 1). rzb d0b channel b ringing voltage zero crossi ng detector output (positive = 1). fltb d1b channel b fault detector output (loop fault = 1). rtb d2b channel b ring-trip detector output (ring-trip = 1). lcb d3b channel b switchhook detector output (off-hook = 1). input data bit input bit definition rza d0a channel a ringing voltage zero cro ssing detector output (positive = 1). flta d1a channel a fault detector output (loop fault = 1). rta d2a channel a ring-trip detector output (ring-trip = 1). lca d3a channel a switchhook detector output (off-hook = 1). rzb d0b channel b ringing voltage zero crossi ng detector output (positive = 1). fltb d1b channel b fault detector output (loop fault = 1). rtb d2b channel b ring-trip detector output (ring-trip = 1). lcb d3b channel b switchhook detector output (off-hook = 1).
preliminary le8575 dual-resistive slic device 21 figure 6. logic diagram (positive logic; flip-flops clocked on high-to-low transition) operating states each channel of the le8575 has four operating states: active, test, powerdown with relay driver rdd on, and powerdown with relay driver rdd off. these states are selected using 2 bits, d0 and d1, via the serial interface according to the truth table shown below. logic input d2 operates the ringing relay driver, rdr, independent of the state of bits d0 and d1; however, the ring-trip detec tor is enabled only when d2 operates the ringi ng relay driver. hence, the ringing relay dr iver is not interchangeable with any of t he other relay drivers. logic input d3 operates the test rela y driver, rdt, independent of the state of bits d0 and d2. active state this is the normal operating state (talk state) of the channel. all circuits are ope rational. the tip drive current source sink s 5.6 ma dc from pt; the ring drive curren t source sinks 5. 6 ma dc into pr. table 16. truth table for d1 and d0 d1 d0 state 1 1 channel active. 1 0 channel test. 01 channel powerdown and relay rdd driver on (rdd low). 00 channel powerdown. relay rdd driver off/rdd high. rza d0 d1 sel q d q q d0a d0a di clk en flta d0 d1 sel q d q q d1a d1a rta d0 d1 sel q d q q d2a rdra lca d0 d1 sel q d q q d3a rdta rzb d0 d1 sel q d q q d0b d0b fltb d0 d1 sel q d q q d1b d1b rtb d0 d1 sel q d q q d2b rdrb lcb d0 d1 sel q d q q d3b rdtb do relay driver relay driver relay driver relay driver relay driver rddb relay driver rdda from ring voltage zero detect circuit from fault detect circuit internal internal from ring-trip circuit internal from loop closure circuit internal 8-bit shift resistor data latches to internal state control combinational logic circuitry indicates external package mode
preliminary 22 le8575 dual-resistive slic device test state this is the test state of the c hannel. it is the same as the active state except that the ring drive current source is saturate d to ground and the tip driver current source is saturated to v bat . this forces the loop-closure and ring-trip detectors to indicate an off-hook. this state is valid only when t he ringing relay is not operated (d2 = 0). powerdown state with re lay driver rdd operated this is the disconnect state of the channel. it is the same as the powerdown state except that relay driver rdd is also operate d. when required, this relay may be used to disconnect the exte rnal dc feed resistors in order to provide a high-impedance termination to the subscriber loop. powerdown state this is the normal idle state (scan state) of the channel. th e loop-closure, ring-trip, and co mmon-mode fault detectors are act ive, but all other circuits are shut down to conserve power. all circ uits common to both channels remain active. the powerdown of channel a does not affect an active channel b and vice-versa. ringing state (d2 = 1) when d2 = 1, the ringing relay driver is activated. the operat ional state of the slic device is unaffected except for the ring- trip and fault detectors. the digital portion of the ring-trip detector is enabled when d2 = 1 (relay drive activated) and disabled when d2 = 0 (relay drive deactivated). the ring-trip detector functi ons properly only when d2 = 1 so that a valid ringing signal (ac and dc) is present. when d2 = 0, the digital portion of the ring-trip detector is bypassed so that most of the ring-trip circuit ca n be tested in the test state. when d2 = 1, the f ault detector is also disabled (flt forced to 0). supervision off-hook detection the off-hook detection threshold is a function of the dc feed resistors r 1 and r 2 , and of a ratio of resistors that are fixed on the le8575 silicon die. thus, when r 1 = r 2 = 300 ? , the off-hook threshold is set at 4 k ? . this relationship is shown in the equation below: where, r t is the loop closure threshold r 1 = r 2 = dc feed resistors = 300 ? where, r t1 and r t2 are internal resistors r t1 = 170 k ? r t2 = 130 k ? thus, r t r 1 r 2 + 1 2 k ? ------------ 1 ? --------------------- - = k r t1 r t1 r t2 + ------------------------- - 0.4333 ? == r t 300 ? 300 ? + 1 2 130 k ? 130 k ? 170 k ? + ------------------------------------------- - ?? ?? ---------------------------------------------------- -1 ? ------------------------------------------------------------- - 3900 ? 4 k ? ==
preliminary le8575 dual-resistive slic device 23 ring-trip threshold figure 7. ring-trip threshold ring-trip threshold is calculated as follows: at ring-trip: if, v bat = v 20 hz (dc) then, r rth = r rf r rf = 1 m ? ; r l (ring-trip) = 6 k ? [avg: 2 k ? & 10 k ? ] ring-trip requirements ? ringing signal: ? voltage: minimum 35 vrms, maximum 100 vrms ? frequency: 17 hz to 23 hz ? crest factor: 1.4 to 2 ? ringing trip: ? 100 ms (typical), 250 ms (v bat = ?33 v loop length = 530 ? ) ?pretrip: ? the circuits in figure 10 will not cause ringing trip loop resistance r l tip ring 300 ? r rf r1 300 ? r rf r rth c rf rtn rtp v rtn (dc) = v bat z v bat 2 -------------- ?? ?? r rf r rth ------------- - ?? ?? 300 ? r l 600 ? + ----------------------------- - ?? ?? v 20 hz (dc) = r rf 2r rth ----------------- 300 ? r l 600 ? + ---------------------------- - = 1 r l 600 ? ----------------- - + ?? ?? r rth = 11 m ? 2r rf c rf 100 ms c rf = 0.047 f
preliminary 24 le8575 dual-resistive slic device figure 8. ring-trip circuits fault detection the dc feed resistors r 1 and r 2 need to be designed to survive lightning surges and to dissipate power associated with a ring ground dc fault and specified ac power cross faults?both in a sneak under and full surge type fault. under certain sustained fault conditions, r 1 and r 2 could fail when they are required to survive. for this reason, a per-channel fault detector is included on the le8575. when the voltage across either r 1 and r 2 is a nominal 36 v (maximum 39 v), the fault detect bit, flt in the serial data output, will go high, as calculated below: flt = 1, if |v tip | > 36 v nominal or |v ring ? v bat | > 36 v nominal, which corresponds to dc power in r 1 or r 2 > 4 w the control logic on the line card detects flt is high and opens an external electromechanical re lay to isolate the resistors f rom the loop, enabling the resistors to survive ex tended power cross. (note the emr is the te st in or test out emr, and this relay is driven by one of the internal relay drivers on the le8575 slic device.) with an external 0.1 f capacitor on pin cflt, a no-fault to fault delay of 10 ns to 30 ms is provided in the fault detector. this prevents transients on tip and ring from tripping the fault detec tor when a fault is not present. there is a release delay (fau lt to no-fault) of 1.6 t to 2.5 t, where t is the no-fault to fault delay time. zero voltage current cross the le8575 provides a bit, rza (and rzb for channel b), in the serial data stream which gives an indication when the ringing voltage is crossing zero. this signal bit may be used in timing the application and removal of the ringing signal. relay drivers six relay drivers, three relay drivers per channel, are included on the le8575 slic device. the output of these drivers are package nodes rdd (a&b), rdr (a&b), and rdt (a&b). drivers rdr (a&b) are controlled by input bits d2 (a&b) on the serial input stream. drivers rdt(a&b) are controlled by input bits d3 (a&b) on the serial inpu t stream. in these cases, a logic 1 on d 2 or d3 activates the respective relay driver. relay drivers rdd (a&b) are contro lled per the truth table (s ee table 2) via bits d0 (a&b) and d1 (a&b). in order to activate driver ddr, d0 = logic 1 and d1 = logic 0. note that with d0 = logic 1 and d1 = logic 0, the slic device is set to the channel powerdown state. relay drivers rdr (a&b) must be used for the ring relay function because the ring-trip detector is enabled only when d2 is high ; that is, when d2 operates the ringing relay driver (rdr). hence, the test and ringing relay drivers are not interchangeable. when relay driver rdd is active, the le8575 is forced into a powerdown state. thus, using rdd with the test-in relay is not appropriate. this relay may be used for test out or as a channel isolation relay. t ip t ip rin g ring ring switch closes <12 ms 200 ? 6 f 10 k ? 2 f 100 ? t ip
preliminary le8575 dual-resistive slic device 25 relay driver rdt is controlled by d3 in the serial bit st ream. logic input d3 operates driver rdt independent of the state of bits d0, d1, and d2. rdt may be used wit h a test-in, test-out, or channel isolation relay. dc characteristics i/v characteristics resistors r 1 and r 2 are the dc feed resistors. r1 is connected from batt ery to ring, and r2 is connected from tip to ground. the dc loop current is fed to the subscriber loop via these re sistors. these resistors will se t the dc i/v template for the lin e circuit, with the i/v template being linear with a ?1/600 ? slope. no constant current region at short dc loops is provided by resistors r 1 and r 2 or the le8575 slic device. the dc tip/ring voltage under open loop conditions is 3.36 v less than battery. in order to drive an on-hook ac signal, the tip and ring voltage must be set to a value less than the batt ery voltage. the amount that the open loop voltage (v oc ) is decreased relative to the battery (v bat ) is referred to as the overhead voltage (v oh ). this overhead voltage is due to 5.6 ma of bias current flow from both the tip and ring current drive amplifier?s flow through resistors r2 and r1, respectively. thus, the overhead is given by: v oh = (r 1 x 5.6 ma) + (r 2 x 5.6 ma) v oh = (300 x 5.6 ma) + (300 x 5.6 ma) = 3.36 v the nominal dc i/v template for the le8575 slic device is shown in figure 9 . figure 9. le8575 slic device i/v template loop length the loop range equation is given by: where, r l is the dc resistance of the subscriber loop. i l is the dc loop current. |v bat | is the magnitude of the battery voltage. v oh is the overhead voltage?nominal 3.36 v. r 1 = r 2 = dc feed resistors = 300 ?. thus, for a nominal ?48 v battery with a minimum 18 ma loop requirement, the loop range will be: r l = 1880 ? 20 80 60 0 5 10 15 20 35 40 0 70 50 30 10 25 30 40 45 50 v t-r (v) i loop (ma) v oc (44.7) v bat (48) r l v bat v oh ? i l ---------------------------------- - r 1 ?r 2 ? = r l 48 v 3.36 v ? 0.018 a ------------------------------------- 3 0 0 ? ?300 ? ? =
preliminary 26 le8575 dual-resistive slic device ac design codec features and selection summary there are four key ac design parameters: ? termination impedance is the impedance looking into the 2-wire port of t he line card. it is set to match the impedance of the telephone loop in order to minimize echo return to the telephone set. ? transmit gain is measured from the 2-wire port to the pcm highway. ? receive gain is done from the pcm highway to the transmit port. ? hybrid balance network cancels the unwanted amount of the receive signal that appears at the transmit port. at this point in the design, the codec needs to be selected. the discrete network between the slic device and the codec can then be designed. below is a brief codec feature and selection summary. first-generation codecs these perform the basic filtering, a/d (transmit), d/a (receive), and -law/a-law companding. they all have an op amp in front of the a/d converter for transmit gain setting and hybrid bal ance (cancellation at the summing node). depending on the type, some have differential analog input stages, differential analog output stages, and -law/a-law selectability. this generation of codec has the lowest cost. it is most suitable for applic ations with fixed gains, termi nation impedance, and hybrid balance. second-generation codecs this class of devices includes a microprocessor interface for so ftware control of the gains and hybrid balance. the hybrid bala nce is included in the device. ac programmability adds application flexibility and saves several passive components. it also adds several i/o latches that are needed in the application. it does not have the transmit op amp, since the transmit gain and hybri d balance are set internally. third-generation codecs this class of devices includes the gains, termination impe dance, and hybrid balance?all under microprocessor control. depending on the device, it may or may not include latches. in the codec selection, increasing software control and flexibil ity are traded for device cost. to help decide, it may be usefu l to consider the following: ? will the application require only one value for each gain and impedance? ? will the board be used in different countries with different requirements? ? will several versions of the board be built? if so, will one version of the board be most of the production volume? ? does the application need only real termination impedance? ? does the hybrid balance need to be adjusted in the field? design equations the following section gives the relevant design equations to choose component values for any desired gain, termination and balance network, assuming a complex termination is desired. comple x termination will be specified in one of the two forms shown below: figure 10. equivalent complex terminations r1 r2 c r2 r1 c (series form) (parallel form)
preliminary le8575 dual-resistive slic device 27 both forms are equivalent to each other, and it does not ma tter which form is specified. the component values in the interface circuit of figure 12 are calculated assuming the paralle l form is specified. if the te rmination impedance to be synth esized is specified in the series form, convert it to the parallel form using the equations below: note that if the termination impedan ce is specified as pure resistive: define the gain constant, k, as follows: where, r x = desired receive (or pcm to tip/ring) gain in db t x = desired transmit (or tip/ring to pcm) gain in db |z t | 1 khz is the magnitude of the complex termination impedance z t being synthesized, calculated at 1000 hz. this equation assumes that the tlp of the code c is 0 dbm referenced to 600 ? . the following equation applies when referring to figure 11 : where, = 2 ? ? = 1000 hz cr 1 r 2 is defined in figure 10 (series form), and r 1 r 1 r 2 + = r 2 r 1 2 r 2 r 1 + r 2 ---------------------------- - = c c 12 r 1 r 2 ------ r 1 r 2 ------ ?? ?? 2 ++ ----------------------------------------- = r 2 r 2 0 and c = c == = k rcv k 0 10 rx/20 for receive gain = k tx 1 k 0 ------ - 10 tx/20 for transmit gain = k 0 z t 1 khz 600 ------------------------ - = = power transfer ratio z t 2 c 2 r 1 r 2 2 r 1 r 2 j r 2 2 c ? ++ 1 2 r 2 2 c 2 + ---------------------------------------------------------------------------------- = z t 2 c 2 r 1 r 2 2 r 1 r 2 ++ 1 2 r 2 2 c 2 + ------------------------------------------------------- - ?? ?? ?? 2 r 2 2 c 1 2 r 2 2 c 2 + -------------------------------- ?? ?? ?? 2 + =
preliminary 28 le8575 dual-resistive slic device figure 11. initial ac interface for complex termination between le8575 slic device and t7504 codec the tip/ring differential current is given by: the voltage at pin xmt is given by: the component values in the ac interface of figure 13 are calculated (for the transmi t and receive gains defined by the respect ive gain constants k rx and k rcv , and for the termination impedance seen in figure 10 ) using the following equations: 600 ? = 2 x 300 ? feed resistors r gx = 2 x k tx (r gx1 + r t1 ) v rn receive interface + ? r t2 r rv2 r hb1 r gx gsx vfxin vfro 1/4 t7504 codec z t/r + ? v t/r i t/r +2.4 v c r 1/2 le8575 r gx1 r rv1 c t r t1 z irp ? + ax v xmt l rp v rn xmt i rp pt pr v bat ts rs v bat r 1 r 2 c 1 resistor module 200 k ? 200 k ? 100 k ? 300 ? 300 ? 100 k ? 1.4 k ? 1.4 k ? dc blocking capacitors (c b ) not shown; c t and c r separate i t/r 200 i rp v rn z irp ---------- - ? ?? ?? = v xmt v t/r ? 2 ------------- - = r rv1 100r 1 k rcv ----------------- = r rv2 100r 2 k rcv ----------------- = c r k rcv c 100 ------------------- - = r gx1 r gx1 r t1 + ---------------------------- - r rv1 100 ------------ - 1 600 -------- - 1 r 1 ------- - ? ?? ?? = c t c 100 -------- -1 r gx1 r t1 ------------ -1 100r 1 r rv1 ----------------- + ?? ?? + = r t2 r 2 c c t -------------- =
preliminary le8575 dual-resistive slic device 29 the 300 ? feed resistors contribute 600 ? to the termination impedance. the te rmination impedance associated with the circuit in figure 13 consists of this inherent 600 ? feeding impedance in parallel with: ? a negative impedance, where, x ? a positive impedance, where, x the negative and positive impedance terms are used to ad just the termination impeda nce from the inherent 600 ? to any complex termination. note in the case of a pure 600 ? dc termination, the two 300 ? feed resistors provide this termination, and components r t1 , r t2 , and c t are not used in the ac interface circuit. using the circuit of figure 13, the ratio of capacitors c t and c r will affect the (transmit and receive) gain flatness, and to a lesser degree the return loss of the line circuit. thus, depending on the requirements, c t and c r may need to be tight tolerance capacitors. if this is the case, capacitors c t and c r may be combined into a single capacitor with a looser tolerance. this is illustrated in figure 12 . figure 12. revised ac interface c t and c r combined into a single capacitor c s to scale c s (higher), increase c t (and decrease r t2 ) by increasing the r gx1 / (r gx1 + r t1 ) ratio by rearranging the circuit in figure 11 and by adding resistor r sc from xmt to irp as shown in the figure below: figure 13. addition of resistor r sc from xmt to irp then, 2 100 -------- - r gx1 r gx1 r t1 + ---------------------------- - r t2 1 j c t ------------- + ? ? ? ? r gx1 r t1 + r t1 ---------------------------- ?? ?? xmt rt2 c t irp c r v fro rrv2 xmt rt2 irp c s = c t + c r v fro rrv2 rrv1 rrv1 ? ? ? r t1 r sc irp c t r t2 xmt vrn r gx1 c b r gx1 r gx1 r t1 + ---------------------------- - r rv1 r sc || () 100 ----------------------------------- 1 600 -------- - 1 r 1 -------- ? ?? ?? r rv1 r rv1 r sc + ---------------------------- - + =
preliminary 30 le8575 dual-resistive slic device once the gains and complex termination are set, if the hybrid bal ance network is identical to the termination impedance, then t he hybrid balance is set by a single resistor (s hown in figure 15) and is computed as follows: the le8575 slic device is ground referenced. however, a +5 v only codec, such as t7504, is referenced to +2.5 v. the le8575 slic device has sufficient dynamic range to accommodate an ac signal from the codec that is referenced to +2.5 v without clipping distortion. with a ?48 v battery, the dc voltage at node xmt will be a nominal ?22 v or ? 4 v. this is the common-mode dc voltage. this will cause a dc current flow fr om the codec to the slic device. this current will not affect ac performance, but it will effectively waste power. to av oid this wasted power consumption, blocking capacitors can be added. the blocking capacitors block the dc path from any low impedance node at the codec to slic device node xmt. blocking capacitors are added to the application diagram in figure 16. after the blocking capacitor c b is added, the above component values may have to be adjusted slightly to optimize performance. the effects of the blocking capacitor are best evaluated and opti mized by circuit simulation. contact your legerity account representative for information on availability of a pspice ? model. figure 16 shows a complete reference design using the le8575 slic device and t8502/3 codec. this line circuit is designed to meet the requirements of the people?s republic of ch ina. the basic ac design parameters are listed below: termination impedance: 200 ? + 680 ? || 0.1 f hybrid balance network: 200 ? + 680 ? || 0.1 f transmit gain: 0 db receive gain: ?3.5 db or ?7.0 db notice that the interface circuit between the le8575 and t8502/3 is designed for a receive gain of ?3.5 db. the t8502 codec offers a pin selectable receive gain of 0 db or ?3.5 db. thus, via logic control, a receive gain of either ?3.5 db or 7.0 db is achieved. the t8502/3 codec is a dual +5 v only codec. when used with the dual le8575 slic device, a complete low-cost, dual-line circuit is achieved. r hb r gx k rcv k tx --------------------------------- = v tip v ring ? () 2 ---------------------------------------- -
preliminary le8575 dual-resistive slic device 31 application diagram the following diagram and table show the basic components required with the le8575 slic device. specific component values are given in cases where the value is fixed. in cases where the value may change (i.e., components that determine the ac interface), the value is not listed but equations to determine these values are given later in this document. table 17. external components required comp. function implementation value attribute* r 1 dc feed protection resistor module 300 ? 1.0%, 2 w ? r 2 dc feed protection resistor module 300 ? 1.0%, 2 w ? r 3 transmit gain resistor module 100 k ? 1.0%, 25 mw ? r 4 transmit gain resistor module 100 k ? 1.0%, 25 mw ? r 5 transmit gain resistor module 200 k ? 1.0%, 25 mw ? r 6 transmit gain resistor module 200 k ? 1.0%, 25 mw ? r 7 protection resistor module 1.4 k ? 2.0%, 0.1 w r 8 protection resistor module 1.4 k ? 2.0%, 0.1 w r 9 battery noise cancellation resistor module 15 k ? 10 mw c vcc v cc filter external 0.1 f 20%, 10 v c vdd v dd filter external 0.1 f 20%, 10 v c bat v bat filter external 0.1 f 20%, 100 v r cbn battery noise cancellation external 301 k ? 1%, 1/16 w c cbn battery noise cancellation external 0.1 f 20%, 100 v c rf ring trip external 0.1 f 20%, 100 v r rf1 ring trip external 1 m ? 20%, 100 v r rf2 ring trip external 1 m ? 1%, 1/16 w r rth ring trip threshold external 11 m ? 1%, 1/16 w c flta fault filter external 0.1 f 20%, 100 v c b1 dc blocking external 0.1 f 20%, 50 v c b2 dc blocking external 0.1 f 20%, 50 v r t1 ac interface external 34 k ? 1%, 1/32 w r t2 ac interface external 7.32 k ? 1%, 1/32 w r gx ac interface external 150 k ? 1%, 1/32 w r gx1 ac interface external 52.3 k ? 1%, 1/32 w r rv1 ac interface external 113 k ? 1%, 1/32 w r rv2 ac interface external 35.7 k ? 1%, 1/32 w c 2 or c s ac interface external 2.7 nf 5%, 10 v r hb1 ac interface external 221 k ? 1%, 1/32 w * power is continuous rms power. ?r 1 /r 2 = 1, with a tolerance of 0.35% for 50 db longitudinal balance, 0.2% fo r 58 db longitudinal balance. fuses on f1 and f2 provide failsafe operation if excessive overvoltage conditions exist on tip and ring. they will not operate if the total power dissipation of th e entire resistor network is >5.0 w at 85 c. ?(r 3 x r 6 )/(r 4 x r 5 ) = 1 with a tolerance of 0. 35% for 50 db longitudi nal balance, 0.2% for 58 db longitudinal balance. r 9 /r 1 = 100 with a tolerance of 0.5%.
preliminary 32 le8575 dual-resistive slic device figure 14. typical application diagram wi th blocking capaci tors (cb) included 18 ptb 13 tsb 12 xmtb 14 rsb 44 clk 43 en 3 di 2 do 1.4 k ? kta 37 38 30 7 +5 d rdta rdra rdda rddb pta tsa 300 ? 200 k ? 28 33 34 xmta 100 k ? xmta kta2 tip test out bus (channel a) kta1 ring 100 k ? 200 k ? 1.4 k ? 32 rsa 27 pra 36 rtpa kra2 1 m ? 0.1 f 35 rtna 1 m ? 300 ? 11 m ? kra1 vrng (ringing v bat 19 prb 10 rtpb 11 rtnb 301 k ? cbna 24 cbnb 22 0.1 f 0.1 f v bat v bat 21, 25 0.1 f agnd 20, 26 v dda 23 +5 a same as channel a same as channel a 4 cfltb 15 rgbnb 16 vrnb 17 irpb c b2 r rv2 r t2 xmta termination/hybrid 200 ? + 680 ? ii 0.1 f 2.7 nf 29 irpa 113 k ? 0.1 f xmta 221 k ? 52.3 k ? r gx 34 k ? 30 vrna vfro(n) vfxin(n) gsx(n) 1/2 t8502/3 codec 15 k ? 31 rgbna 0.1 f 42 cflta serial interface buses to control logic 8 rdrb 9 rdtb 5, 41 v ddd 0.1 f dg 6, 40 dgnd (office battery) thick film resistor r x = ?3.5 db/?7.0 db r rth r f2 r 2 r 8 r 6 r 4 r 3 r 5 r f1 thick film resistor c rf r 1 module supply) module r 7 le8575 r 9 kta kta ktb ktb ktb 35.7 k ? 7.32 k ? 0.1 f 150 k ? r t1 r rv1 c s = c t + c r r gx1 c b1 r hb2 c vdd c flta t x = 0 db gs gain c cbn c bat c vcc r cbn select
preliminary le8575 dual-resistive slic device 33 physical dimensions 44-pin plcc dwg rev. an; 8/00 plcc 044 plcc 044
the contents of this document are provided in connection with l egerity, inc. products. legerity makes no representations or war ranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descri ptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellect ual property rights is granted by this pub lication. except as set forth in legerity's standard terms and conditions of sale, legerity assumes no liab ility whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitn ess for a particular purpose, or infringement of any intellect ual property right. legerity's products are not designed, intended, authorized or warra nted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any ot her application in which the failure of legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur. leger ity reserves the right to discontinue or make changes to its products at any time without notice. ? 2004 legerity, inc. all rights reserved. trademarks legerity, the legerity logo and combinations thereof, and slac are trademarks of legerity, inc. other product names used in this publication are for identifica tion purposes only and may be trademarks of their respective com panies.
4509 freidrich lane austin, texas 78744-1812 telephone: (512) 228-5400 fax: (512) 228-5508 north america toll free: (800) 432-4009 to find the legerity sales office nearest you, visit our website at: http://www.legerity.com/sales or email: sales@legerity.com to download or order data sheets, application notes, or evaluation tools, go to: www.legerity.com/support for all other technical inquiries, please contact legerity tech support at: techsupport@legerity.com or call +1 512.228.5400. tm

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